1. Field of Invention
The present invention relates to a manufacturing method for a flash memory cell. More particularly, the present invention relates to a manufacturing method for a split-gate flash memory cell.
2. Description of Related Art
Read only memory (ROM) is a kind of non-volatile memory that can store and retain data even when the power is off. Erasable programmable ROM (EPROM) further expands the application of ROM by introducing the functions of memory erase and rewrite. However, erasing data from an EPROM requires ultraviolet light, and hence packaging cost is comparatively higher. Moreover, memory erase operation will wipe out all the stored data residing inside the EPROM. Therefore, whenever data update is required, every bit of data must be rewritten back to the EPROM, which is rather time-consuming.
Another type of permanent memory that allows changes to a part of the stored data without the need for rewriting everything is the electrically erasable programmable ROM (EEPROM). For EEPROM, data erase and write operations can be conducted in a bit-by-bit fashion. Moreover, data store, read and erase operations can be carried out repeatedly without limitations. A flash memory is an improved version of EEPROM having the same structure as a conventional EEPROM, except that the flash memory is erased block-by-block rather than bit-by-bit. Hence, the speed of operation for a flash memory is exceptionally fast, and a memory erase operation can be finished, for example, within one or two seconds. Because of the time and cost saving benefits, flash memories are now widely used in data storage systems.
In general, the gate of a flash memory cell includes a two-layer structure. One of the layers, known as a floating gate, is a polysilicon layer whose function is to store electric charges. The second layer is known as a control gate and is used to control the storage and retrieval of data. The floating gate is located underneath the control gate, and is in a "floating" state because it is not connected with any other circuit components. On the other hand, the control gate is connected to the word line. There are many articles related to flash memory. For example, Naruke et al. has published an article in Technical Digest of IEEE Electronic Device Meeting, 1988 with the title "A new flash-erase EEPROM cell with a sidewall select-gate on its source side". In the article, an improved flash memory model is described.
FIGS. 1A and 1B are the respective cross-sectional and perspective view of a flash memory cell structure according to the publication by Naruke et al. As shown in FIGS. 1A and 1B, a floating gate 11 and a control gate 12 are formed above a semiconductor substrate 10. A select gate 13 is formed on the side of the floating gate 11 and the control gate 12. The floating gate 11, the control gate 12 and the select gate 13 together constitute a split-gate structure 14. On two sides of the stacked split-gate 14 are ion-doped source region 15 and drain region 16, respectively. The select gate is located on the side of the source region 15, and is formed by an etching back operation. Hence, the select gate 13 is parallel to the control gate 12. The characteristic of this type of flash memory cell is the utilization of select gate 13 to prevent abnormal out-leaking of current, which may result in over-erasing, so that a normal memory operation is maintained. However, because the select gate and the control gate are parallel to each other, problems regarding the design of device may arise. Furthermore, the length of a select gate must be fixed. Therefore, properties of a memory cell are difficult to adjust, and may cause serious interference during data programming.
To resolve the above problems, Y. Ma et al. published an article in VLSI technical conference in 1994 with the title "A novel high density contactless flash memory array using split-gate source-side injection cell for 5V-only application". In the article, another improved flash memory structure is described.
FIG. 2 is a cross-sectional view showing the improved flash memory cell structure according to the publication by Y. Ma et al. As shown in FIG. 2, a floating gate 21, a control gate 22 and a select gate 23 that constitutes a stacked split-gate 24 are formed above a semiconductor substrate 20. On each side of the split-gate 24, ion-doped source region 25 and drain region 26 are formed in the semiconductor substrate 20. The select gate 23 is formed such that it covers the top and the sides of the control gate 22. This type of select gate structure decreases data programming interference problems. However, the level of precision needed in the photolithographic process for forming the select gate 23 is very high, and so a large amount of space is consumed.
In addition, data is stored in an EEPROM by tunneling electrons into the floating gate. During programming, voltages are applied to the control gate and the source/drain regions, and the electrons tunnel through the gate oxide layer to finally end up in the floating gate. Therefore, thickness of the gate oxide layer is critical for the whole tunneling operation. Moreover, the required programming voltages depend very much on the thickness of the gate oxide layer, too. If the gate oxide layer is too thin, too much current may leak out causing a lowering of stability for the memory.
In light of the foregoing, there is a need to provide an improved method of manufacturing split-gate flash memory.